In recent years important advances have been made in increasing the power efficiency of analogue-to-digital converters. Particularly efficient implementations are based on a successive approximation register (SAR) architecture.
In a typical successive approximation register analogue-to-digital conversion (SAR ADC) architecture the input voltage is compared against a digital-to-analogue converter (DAC) output voltage using a comparator in several cycles. The input signal first goes through a sample and hold block. The SAR search logic block executes a search algorithm, which typically performs a binary search. In the first cycle the input is compared against the middle of the ADC range. From the comparator output the most significant bit (MSB) can be determined. In the next cycle bit MSB-1 is determined and so on. A conversion to N bits normally requires N cycles. The SAR ADC is low in cost and consumes low operating power. The excellent power efficiency of the SAR converter can be attributed both to the inherent efficiency of the binary search algorithm and the simplicity of the required hardware.
High resolution SAR analogue-to-digital converters (ADCs) (>10bit) with very low power and MS/s sampling rates are popular in wireless sensor node to obtain robust wireless communication links. However, the comparator becomes one of the most power-hungry components in this resolution. However, the intrinsic accuracy (DAC matching) of a SAR ADC is limited up to 10 or 12 b in modern CMOS technologies. Scaling up the device dimensions can improve matching but deteriorates power-efficiency and speed.
A conventional SAR ADC scheme is depicted in FIG. 1. A sample and hold circuit is used, as well as a comparator, a DAC, and a digital SAR controller. The analogue signal Vin enters the sample and hold (S/H) circuit where the signal simply is sampled and held to provide a buffer for the A/D converter. Vin is compared to a reference voltage Vref at the comparator input. The digital comparison result goes to the SAR controller block comprising the search logic. The controller block adjusts the digital control signals in order to narrow the compared voltages. An adjusted digital signal is provided at an output to a digital-to-analogue converter (DAC). This signal is converted to an adjusted Vref, which is compared to Vin in the comparator. A common implementation of the DAC uses an array of capacitors which are controlled by the SAR controller block.
Analogue imperfections in the SAR ADC converters such as DAC mismatch and comparator offset, introduce errors that are typically mitigated through a calibration. The calibration measures and compensates for the analogue imperfections in the SAR A/D converters. However, most calibrations are implemented off-chip, as the power for the calibration circuit is relatively high when implemented on-chip. Foreground calibration is an alternative choice but it may be sensitive to environment and can introduce additional effort (e.g., manual effort) to perform the calibration.
The comparator is a power-hungry component in high-resolution SAR ADCs. To save power, two-mode comparators have been introduced (see “A 0.7V 7-to-10 bit 0-to-2 MS/s Flexible SAR ADC for Ultra Low-Power Wireless Sensor Nodes”, P. Harpe et al., IEEE Eur. Solid-State Circuits Conf., September 2012). The comparator works in low-power mode for coarse comparisons and switches to high-precision mode for fine comparisons, resulting in significant energy reduction. However, as the offset in these two modes might be different, this scheme can introduce a dynamic offset, which may impede the conversion accuracy. Besides, the comparator offset is sensitive to environmental changes (e.g., temperature). For that reason, an offset calibration is implemented that aims to equalize the comparator offset in the two modes to similar levels. However, due to the absence of error detection capability, the offset error can only be corrected manually by iteratively tuning the capacitor value and observing the measured ADC performance.
The paper “A 820 μW 9b 40 MS/s Noise-Tolerant Dynamic-SAR ADC in 90 nm Digital CMOS” (V. Giannini et al., ISSCC Dig. Tech. Papers, pp. 238-239, February 2008) presents an ADC with two comparators with different noise performance to reduce the overall power consumption. It uses two comparators with different input-referred noise. Due to the use of two separate comparators, there are two independent offsets. The offset difference between the two comparators is corrected by loading the calibration settings through a serial register.
However, in these references, the comparator offset error cannot be directly measured. As a result, the comparator offset is compensated manually. Hence, there is a desire for a low-power fully automated on-chip background calibration approach for correcting comparator offset.